The increasing complexity and shrinking size of integrated circuit devices has created a need for each device to have a larger number of input/output points (I/Os). Flip chip technology is being utilized to allow more input/output I/Os on an integrated circuit device. Flip chip technology utilizes solder bumps instead of wires to connect contact pads on an integrated circuit (IC) device to contact pads on an IC package or to contact pads on a circuit board.
Solder bumps are created on IC devices while the IC devices, also referred to as die, are still on a semiconductor wafer. FIG. 1 is a depiction of a semiconductor wafer 102 that includes multiple die that are similar to the uppermost and leftmost die 104. The process of creating the solder bumps begins after contact pads have been formed on the top surface of the semiconductor wafer. In one known technique, after the contact pads have been formed, an under bump metal layer is deposited on top of the semiconductor wafer (including the contact pads) and covered with a protective layer of photoresist. The under bump metal layer is placed on top of the semiconductor wafer because the solder material that is used to form the solder bumps does not readily adhere to the contact pads. The protective layer of photoresist is then patterned and removed in the areas above the contact pads utilizing known photolithographic processes. Removing portions of the photoresist in the areas above the contact pads exposes the under bump metal layer that is above the contact pads. Once the under bump metal layer is exposed above the contact pads, solder material is formed over the exposed portions of the under bump layer. One technique for depositing solder material onto a semiconductor wafer involves electroplating the solder material onto the exposed portions of the under bump metal layer. Once the solder material is plated onto the exposed under bump metal layer, the protective layer of photoresist and the unneeded portions of the under bump metal layer are removed. The plated solder material subsequently is put through a reflow process that forms the solder material into smooth solder bumps.
In order to connect the solder bumps to an IC package or to a circuit board, it is important that the solder bumps are formed with a uniform height across a semiconductor wafer. It is hard to electroplate solder bumps of uniform height all the way across a wafer. One problem with electroplating that contributes to solder bumps being formed at a non-uniform height is the uneven distribution of plating current density across a wafer. The uneven distribution of plating current density causes a thicker layer of solder to be plated over areas where the current density is higher and a thinner layer of solder to be plated over areas where the current density is lower.
Because of the current flow characteristics around a wafer, current density is typically higher around the outer edge of the pattern of die that is present on a semiconductor wafer. Crowding of current lines occurs around the outer edge of the pattern of die and creates a thicker plating layer on the die at the outer edge of the pattern of die. The creation of a thicker plating layer around the outer edge of the pattern of die, known as an "edge effect," results in solder bumps that are not uniform in height across a semiconductor wafer. When solder bumps fall outside of acceptable height range boundaries, the affected die on a wafer must be reworked or scrapped, reducing the efficiency of the production process. The edge effect can occur on a per wafer basis, such that solder bump height varies across a wafer, and on a per die basis, such that solder bump height varies across the surface of a single die.
One technique that has been considered to counteract the edge effect that is experienced when electroplating solder material onto semiconductor wafers involves continuing the IC layout pattern to the edge of the wafer. For example, FIG. 2 depicts a semiconductor wafer 202 that has an IC layout pattern that includes die that continue to the edge of the semiconductor wafer. Each complete square on the semiconductor wafer represents a complete die (e.g., die 204) and each partial square on the semiconductor wafer represents a partial die (e.g., 206). During processing of the semiconductor wafer, the under bump metal layer and the solder bumps are deposited out to the edge of the wafer in a repeating pattern. Because the solder bumps are deposited out to the edge of the semiconductor wafer, the edge effect is experienced by the outer lying die. As a result, the outer lying die exhibit some thicker solder plating while the inner die experience more uniform thickness of solder plating. However, because the outer lying die are usually only portions of complete die, the outer lying die are scrapped regardless of solder bump height. Although extending the IC layout pattern out to the edge of the semiconductor wafer may work well to minimize the number of complete die that are subjected to the edge effect, it can create other wafer handling and processing problems.
In view of the increased reliance on flip chip technology, there exists a need for a technique that allows solder bumps of uniform height to be plated onto a semiconductor wafer.